https://jasper-aa64.github.io/tags/x86/Recent content in X86 on JasperHugoen-usTue, 15 Sep 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/memory-ordering-false-sharing-dependency-chains/Tue, 15 Sep 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/memory-ordering-false-sharing-dependency-chains/The store buffer and the cache-coherence protocol are one piece of hardware, but they create two unrelated engineering problems. One is correctness: does a thread see the right value, in the right order — solved by memory_order and release/acquire pairing. The other is performance: how many cycles does touching shared or dependent data cost, even when every value read is already correct — solved by cache-line layout and instruction scheduling. Conflating the two is the single most common confusion in this part of systems programming.