https://jasper-aa64.github.io/tags/simd/Recent content in Simd on JasperHugoen-usThu, 15 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/simd-vectorization-intrinsics/Thu, 15 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/simd-vectorization-intrinsics/One instruction computes a row of numbers only if the compiler knows how wide a register it may use, is sure nothing overlaps, and is allowed to reorder; when it can’t get all three, intrinsics let you write it yourself, at the cost of alignment, instruction-set detection and the last few digits of the result.https://jasper-aa64.github.io/posts/loop-optimization/Mon, 12 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/loop-optimization/A dot-product loop reports “vectorized” at -O3, yet its four additions still wait on each other: floating-point addition isn’t associative, so the compiler won’t reorder it. What loop optimization really asks of you is to spot what blocks the compiler, and to make the changes it won’t make for you.https://jasper-aa64.github.io/posts/low-latency-memory-latency-bandwidth/Fri, 09 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-memory-latency-bandwidth/One memory access takes about 100 ns and brings back 64 B. One at a time, that’s 0.64 GB/s, yet one core reading sequentially gets 15–60 GB/s. The missing factor is the number of requests in flight. Whether the next load’s address has to wait for this load decides whether your code is latency-bound or bandwidth-bound.