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2 posts

Low-Latency Systems Development #6 41 min read

Alignment, Layout, and Cache and DRAM Geometry

An access never pays for bytes; it pays for cache lines, and the address decides which lines, which cache set they compete for, and which DRAM channel and bank they live on. Part 1 is alignment: why a double aligned to 8 never …

Low-Latency Systems Development #1 17 min read

CPU Isolation and NUMA

The enemy of a low-latency system is jitter, not the mean. The goal is to make your hot thread the only thing that will ever run on its core: pinning kills migration cost, the isolation stack evicts the tick / RCU / interrupts one …