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Low-Latency Systems Development Topic 22 min read

A Cache Case Study: Repricing 64 Options per Tick

One tick touches 140 cache lines, and most of the time goes into waiting for them. None of the four steps changes the computation; they change when data arrives, where it lands and who holds it: put the misses in flight together, …

Low-Latency Systems Development Topic 36 min read

Memory Latency and Bandwidth

One memory access takes about 100 ns and brings back 64 B. One at a time, that’s 0.64 GB/s, yet one core reading sequentially gets 15–60 GB/s. The missing factor is the number of requests in flight. Whether the next load’s address …