https://jasper-aa64.github.io/tags/linux/Recent content in Linux on JasperHugoen-usWed, 04 Nov 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-context-switch-page-table-tlb/Wed, 04 Nov 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-context-switch-page-table-tlb/Threads are lighter than processes because the TLB and caches stay usable after the switch, not because the switch itself is cheaper. The TLB has no MESI: when any thread in a process changes the page tables, every core still holding that page table gets interrupted, and pinning and isolcpus cannot prevent it, so once a hot-path process is running its address space is read-only.https://jasper-aa64.github.io/posts/scheduling-priority-inversion-kernel-tuning/Thu, 29 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/scheduling-priority-inversion-kernel-tuning/Who runs first and for how long: scheduling classes and time slices, three traps of real-time priorities, two fixes for priority inversion, why HFT often skips PREEMPT_RT, and which knobs a low-latency box turns from BIOS to sysctl.https://jasper-aa64.github.io/posts/low-latency-perf-profiling/Thu, 22 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-perf-profiling/stat for the totals, record and report to find the function holding 98% of the samples, annotate to see every sample land on the instruction after an add: a chain of adds, each waiting for the last, and splitting it four ways is 3.3 times faster. Without hardware counters, cpu-clock sampling still works; if the report shows only addresses, check the symbol table and the path the program runs from.https://jasper-aa64.github.io/posts/cpu-affinity-core-isolation-numa/Wed, 09 Sep 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/cpu-affinity-core-isolation-numa/The enemy of a low-latency system is jitter, not the mean. The goal is to make your hot thread the only thing that will ever run on its core: pinning kills migration cost, the isolation stack evicts the tick / RCU / interrupts one layer at a time, disabling SMT and locking frequency removes the core’s own variability, and share-nothing sidesteps NUMA entirely.