https://jasper-aa64.github.io/tags/cache/Recent content in Cache on JasperHugoen-usTue, 20 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-cache-case-study/Tue, 20 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-cache-case-study/One tick touches 140 cache lines, and most of the time goes into waiting for them. None of the four steps changes the computation; they change when data arrives, where it lands and who holds it: put the misses in flight together, ask for the next batch early, hand back lines that are dead after one read, read one line less across the handoff, and leave the lines the other core will read in L3.https://jasper-aa64.github.io/posts/alignment-layout-cache-dram-geometry/Sun, 04 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/alignment-layout-cache-dram-geometry/An access never pays for bytes; it pays for cache lines, and the address decides which lines, which cache set they compete for, and which DRAM channel and bank they live on. Part 1 is alignment: why a double aligned to 8 never straddles a line, why padding exists for arrays, alignas on a type versus a member, and how to get 64-byte and 2 MiB alignment on the heap. Part 2 is layout: lines per access, AoS versus SoA, and denormalization as a way to cut a dependency chain. Part 3 goes into the hardware: L1 picks a set from address bits 6–11, so data 4 KiB apart competes for 8 slots however empty the cache is (measured on an M1); a DRAM bank has one row buffer, 14 ns on a hit and 41 ns on a conflict; a column walk loses at five layers; refresh adds a P99 tail software can’t remove; and channels balance only when the hot stride is coprime with the channel count.