#Cache-Coherence

2 posts

Low-Latency Systems Development Topic October 4, 2026 14 min read

MESI Cache Coherence

MESI enforces one rule: a cache line has either one core that may write it or any number of cores that may only read it, never both. The four states are the answers to two questions — does anyone else hold this line, and have I …

#cpp #mesi #cache-coherence #false-sharing #atomics

Low-Latency Systems Development #2 September 15, 2026 25 min read

Memory Ordering and Cache Lines

The store buffer and the cache-coherence protocol are one piece of hardware, but they create two unrelated engineering problems. One is correctness: does a thread see the right value, in the right order — solved by memory_order …

#cpp #memory-model #atomics #cache-coherence #false-sharing