<?xml version="1.0" encoding="utf-8" standalone="yes"?><rss version="2.0" xmlns:atom="http://www.w3.org/2005/Atom"><channel><title>Avx2 on Jasper</title><link>https://jasper-aa64.github.io/tags/avx2/</link><description>Recent content in Avx2 on Jasper</description><generator>Hugo</generator><language>en-us</language><lastBuildDate>Thu, 15 Oct 2026 00:00:00 +0000</lastBuildDate><atom:link href="https://jasper-aa64.github.io/tags/avx2/index.xml" rel="self" type="application/rss+xml"/><item><title>Trading System Notes #15: SIMD Vectorization and Intrinsics</title><link>https://jasper-aa64.github.io/posts/simd-vectorization-intrinsics/</link><pubDate>Thu, 15 Oct 2026 00:00:00 +0000</pubDate><guid>https://jasper-aa64.github.io/posts/simd-vectorization-intrinsics/</guid><description>One instruction computes a row of numbers only if the compiler knows how wide a register it may use, is sure nothing overlaps, and is allowed to reorder; when it can&amp;rsquo;t get all three, intrinsics let you write it yourself, at the cost of alignment, instruction-set detection and the last few digits of the result.</description></item></channel></rss>