https://jasper-aa64.github.io/tags/atomics/Recent content in Atomics on JasperHugoen-usMon, 26 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/wait-free-sticky-counter/Mon, 26 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/wait-free-sticky-counter/Wait-free is not a faster lock-free: it turns a failed CAS from “try again” into “I come after you”, which bounds every thread’s steps, at the cost of more atomics and code that is harder to get right.https://jasper-aa64.github.io/posts/spinlock-implementation/Wed, 21 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/spinlock-implementation/Whether a spinlock is fast depends on what its waiters do: if every attempt is a read-modify-write, they drag the lock’s line back and forth. Read before you grab, put PAUSE in the loop, back off after losing, and waiting costs the holder almost nothing.https://jasper-aa64.github.io/posts/low-latency-mesi-cache-coherence/Sun, 04 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/low-latency-mesi-cache-coherence/MESI enforces one rule: a cache line has either one core that may write it or any number of cores that may only read it, never both. The four states are the answers to two questions — does anyone else hold this line, and have I changed it? — and every cost in the protocol comes from moving data between layers or waiting for another core to confirm. False sharing, a cached queue cursor and a producer that slows down as readers join are all the same state machine. Coherence still doesn’t make a multi-word read atomic, and it says nothing about the order of writes to different addresses; that is what fences are for.https://jasper-aa64.github.io/posts/spmc-shared-memory-broadcast-ring/Sun, 04 Oct 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/spmc-shared-memory-broadcast-ring/Market data has one producer and several consumers, each of which must see every message, and the producer is the hot path that may not wait for anyone. The answer is a broadcast ring: every slot carries its own sequence stamp, readers keep private cursors, and the producer overwrites the oldest slot without ever reading reader state. The price moves to the readers — overruns are silent, a re-check after reading can’t catch a half-written slot unless the writer invalidates the stamp first, and readers that catch up take the line the producer writes next, so every flat-out write costs more. Moving the ring into shared memory adds three more rules: nothing inside it may be a pointer, the first lap pays a page fault every 32 messages, and a restarted reader loses everything unless it saved its cursor.https://jasper-aa64.github.io/posts/lock-free-queue-logger-micro-batching/Sun, 20 Sep 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/lock-free-queue-logger-micro-batching/A lock-free SPSC queue works because every shared variable has exactly one writer: each side updates only its own counter and merely reads the other’s. The rest is keeping that property from being quietly undone — a shared element count both cores fight over (subtract two counters instead), a full-check that reads the other core on every call (cache the other side’s cursor, which can only be wrong in the safe direction), a mirrored mapping that removes the wrap-around seam, and a logger that pushes one character per slot (thirty slots for one log line, five as text runs). It ends with the vocabulary that keeps lock-free claims honest: SPSC is wait-free only through a fail-fast interface, finite steps are not finite time, and a bounded queue must always choose between dropping and blocking.https://jasper-aa64.github.io/posts/memory-ordering-false-sharing-dependency-chains/Tue, 15 Sep 2026 00:00:00 +0000https://jasper-aa64.github.io/posts/memory-ordering-false-sharing-dependency-chains/The store buffer and the cache-coherence protocol are one piece of hardware, but they create two unrelated engineering problems. One is correctness: does a thread see the right value, in the right order — solved by memory_order and release/acquire pairing. The other is performance: how many cycles does touching shared or dependent data cost, even when every value read is already correct — solved by cache-line layout and instruction scheduling. Conflating the two is the single most common confusion in this part of systems programming.