Whether ⑥ can happen depends on which reorderings the CPU allows
data, read later, is older than ready, read earlier: a load-load reordering. x86 forbids it; the hardware makes ⑥ read 42. ARM allows it: ready must be read with acquire so later loads wait for the invalidation. ARM also lets two stores reorder, so ready may become visible before data, and the store to ready needs release. On x86 the code is still wrong: ready isn't atomic, so the compiler may hoist the load out of the loop or swap the two stores. Fix: std::atomic<bool> ready, release store, acquire load.